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Serial peripheral interface (SPI)
RM0008
23.2.2
I 2 S features
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Simplex communication (only transmitter or receiver)
Master or slave operations
8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 96 kHz)
Data format may be 16-bit, 24-bit or 32-bit
Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
Programmable clock polarity (steady state)
Underrun flag in slave transmission mode and Overrun flag in reception mode (master
and slave)
16-bit register for transmission and reception with one data register for both channel
sides
Supported I 2 S protocols:
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–
–
–
I 2 S Phillips standard
MSB-Justified standard (Left-Justified)
LSB-Justified standard (Right-Justified)
PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
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Data direction is always MSB first
DMA capability for transmission and reception (16-bit wide)
Master clock may be output to drive an external audio component. Ratio is fixed at
256 × F S (where F S is the audio sampling frequency)
In connectivity line devices, each I 2 S (PLL2 and PLL3) has a dedicated PLL to
generate an even more accurate clock.
Note:
588/995
In connectivity line devices, SPI2 and SPI3 both support I2S Master and Slave mode
operations.
In high-density devices, SPI2 supports I2S Master and Slave mode operations whereas
SPI3 only supports I2S Master mode operations.
Doc ID 13902 Rev 9
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